Publications

2025

1. SYSTEM AND METHOD FOR WIRELESS POWER AND DATA TRANSFER FOR BACK TELEMETRY BETWEEN TRANSMITTER AND RECEIVER

   Reyya Kiran, and  Abhishek Kumar

   561819, Mar 2025

2024

1. A FREQUENCY DIVISION DUPLEXER (FDD) TO FACILITATE WIDEBAND ISOLATION OF TRANSMITTING AND RECEIVING FREQUENCY

   H S Trinath Tammisetti, and  Abhishek Kumar

   557058, Dec 2024

2. 

   A Tunable FDD Duplexer using Electrical Balance with N-Path Filters

   H S Trinath Tammisetti, Nikhil Malgundkar, and Abhishek Kumar

   In 2024 IEEE International Symposium on Circuits and Systems (ISCAS), May 2024

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   This work presents a self-interference cancellation front-end for FDD systems. The front end utilizes an electric-balance hybrid coupler connected to N-path filters having equal and opposite reflection coefficients. This arrangement allows for wideband transmitter (Tx) to receiver (Rx) isolation with a very close offset without incurring loss present in conventional electrical balance front-ends. In addition, Tx-Rx isolation in the proposed front end is insensitive to antenna impedance. We have simulated the N-path filters using transistors from a 65 nm CMOS process. Simulation of the entire front-end shows a tunable center frequency from 800 MHz to 1.5 GHz with wideband Tx-Rx isolation exceeding 40 dB, even with a 50 MHz Tx-Rx frequency offset. The insertion loss in the Tx and Rx paths is 1.4 dB and 3 dB respectively.

3. 

   A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity Mode

   Gopikrishna Vijayakumar, Alok Joshi, and Abhishek Kumar

   In 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Jan 2024

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   This work presents a dual-input direct-conversion receiver operating in 1.6-2.1 GHz and 2-2.5 GHz, respectively, with a 2-dB NF featuring 15 gain modes, including a high linearity circuit. This work employs two separate input elements to increase the matching bandwidth while reusing the rest of the receiver resulting in area savings. Around 70 dB gain tuning is designed, achieving a maximum IIP3 of 14.37 dBm while keeping LO leakage below -115 dBm at the antenna. The receiver is designed in a 28 nm CMOS process, and post-layout simulations were performed in the presence of ESD circuitry and FCBGA package model. The receiver occupies 0.33 mm^2 while drawing a maximum of 47.7 mW from a 0.9 V.

2023

1. 

   A Single-Turn Inductor based Compact and Wide-Tuning LC-VCO using Dual-Resonant Modes

   Ritesh Sachdeva, and Abhishek Kumar

   In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2023

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   This work presents a wide tuning range LC-VCO (Voltage controlled oscillator) covering 6.53 GHz to 10.85 GHz. Novelty of the work lies in using just a single-turn inductor for dual-mode resonance while avoiding any switch in the supply path. The VCO has been designed in 65 nm CMOS technology occupying an active area of 0.0492 mm2 and having a tuning range of 49.7%. The proposed VCO has more than 2x lower area than other wide-tuning LC VCOs in similar frequency range. The post-layout simulated FOMA for this VCO is between 197.18 dBc/Hz to 198.98 dBc/Hz.

2022

1. Method and system for interference cancellation in MIMO wireless system

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   US11239878B2, Feb 2022

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2. Sampler in a full-duplex system and method of sampling received signal

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   US11303320B2, Apr 2022

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2021

1. A DISTRIBUTED CIRCUIT FOR CANCELLING SELF-INTERFERENCE IN A FULL DUPLEX COMMUNICATION SYSTEM USING ELECTRICAL BALANCE

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   356249, Jan 2021

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2. A 4-bit Bidirectional Phase Shifter for 3GHz S-Band Applications

   Madhavi Kadam, Abhishek Kumar, and Sankaran Aniruddhan

   In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2021

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   This paper proposes a transmission-line based bidirectional reflection-type phase shifter for the 2.5 to 3.2 GHz frequency band. Open and short reflective loads are used to double the available phase shift and reduce insertion loss. The transmission line is implemented using inductors and MOS switches in a 65 nm RF CMOS process. This work achieves a total phase shift of 180° with phase resolution of 22.5° at 2.85 GHz and rms error of 1.2°. The insertion loss of the phase shifter is 5.7 dB and the loss variation is less than 0.3 dB.

2020

1. Reply to Comments on “An Asymmetric 2.4 GHz Directional Coupler Using Electrical Balance”

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   IEEE Microwave and Wireless Components Letters, Aug 2020
2. An Unconditionally Stable 28 GHz 18 dB Gain LNA Employing Current-Reuse

   Madhavi Kadam, Sankaran Aniruddhan, and Abhishek Kumar

   In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Oct 2020

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   In this paper, the design and analysis of a 28 GHz CMOS Low noise differential amplifier is discussed. A current reuse technique is used to minimize power consumption by stacking two common source amplifiers. The proposed LNA is designed in a 65nm RF CMOS process to achieve an output matched voltage gain of 18.5 dB and minimum Noise figure(NF) of 4.6 dB. The LNA consumes 10mW from a 1.2 V power supply and exhibits an input-referred 1dB compression point of -16.1 dBm. The LNA is designed using transmission lines, inductors, high-Q capacitors, and a transformer, and occupies a total area of only 0.33 mm2.

3. 

   A 28GHz Reflective-Type Transmission-Line-Based Phase Shifter

   Madhavi Kadam, Abhishek Kumar, and Sankaran Aniruddhan

   IEEE Transactions on Circuits and Systems I: Regular Papers, Dec 2020

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   This work presents a 28GHz reflection type transmission-line (TL) based phase shifter. The proposed architecture employs a completely passive approach to double the phase shift achievable using a TL when compared to conventional architectures. The phase shifter, along with a preceding low noise amplifier and buffer, is implemented in a 65nm CMOS process. The fabricated chip achieves a measured phase resolution of 11.25° at 28GHz, with an rms error of 3° and a total phase shift of 180°. The insertion loss of the phase shifter alone is 17dB. The active area of the entire phase shifter, including LNA and buffer is 0.41mm2.

2019

1. Single Ended and Differential Passive RF Impedance Tuners for 2.4 GHz ISM Band Applications

   Ram Krishna, Abhishek Kumar, and Sankaran Aniruddhan

   In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2019

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   This paper presents the design of two electronically tunable passive RF impedance tuners operating between 2.4 GHz and 2.5 GHz. Theoretical analysis and simulation were performed on two pi matching networks in cascade which helped in increasing the load voltage standing wave ratio (VSWR) coverage. The linearity of the optimized single ended matching network was improved by converting it into a differential structure. Both the impedance tuners based on this theory were fabricated on a two layered FR4 PCB. The fabricated single ended tuner was tested for load impedance variation up to VSWR ≤ 9.5 wherein insertion loss stayed between 0.4 dB and 5.1 dB. The differential network was tested for load impedances up to VSWR ≤ 6 wherein an insertion loss between 0.6 dB and 6.1 dB was obtained. The measured IIP3 of the differential and single ended networks were 37.4 dBm and 34.2 dBm respectively.

2. 

   A Compact +10/+5 dBm 800/2600 MHz LTE Driver Amplifier With Ground-Bounce Reduction

   Anantha Melavarige, Abhishek Kumar, and Sankaran Aniruddhan

   IEEE Transactions on Circuits and Systems II: Express Briefs, Jun 2019

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   A reconfigurable, compact, dual-band radio frequency driver amplifier (DA) is presented. The proposed DA operates in the 800 and 2600 MHz LTE bands using a single inductor for both bands. The single-ended DA demonstrates a ground bounce reduction technique using a series-LC resonant network at the source of the amplifying device, which also improves overall gain. It is fabricated on a TSMC 65-nm CMOS process and measurement results show that it is capable of delivering up to 16.5/14.5 dBm saturated power at a drain efficiency of 35.7%/32.2%. When driven with a 10 MHz 16-QAM LTE signal, it delivers a modulated power of +10/+5 dBm at a drain efficiency of 14.5%/7.5%, and exhibits an ACPR of -40 dBc. The DA consumes a power of 69/42.2 mW from a 2.5-V supply, and occupies an overall area of 0.48 mm2.

3. 

   A 2.35 GHz Cross-Talk Canceller for 2×2 MIMO Full-Duplex Wireless System

   Abhishek Kumar, and Sankaran Aniruddhan

   In 2019 IEEE MTT-S International Microwave Symposium (IMS), Jun 2019

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   A reciprocal network to mitigate cross-talk induced interference (CI) in a 2×2 Multiple Input Multiple Output (MIMO) wireless node operating in same-channel full-duplex (SCFD) mode is proposed. Reciprocal nature of channel between the two antennas of the MIMO node is exploited to simplify the design of cancellation network. A canceller board is designed and fabricated on an FR4 PCB to test the proposed technique. Measurements on the board connected to a dual-port antenna mounted in lab environment show CI cancellation of more than 55dB in 20MHz bandwidth around 2.35 GHz. Self interference (SI) is also cancelled to more than 35dB in the 20 MHz bandwidth. Measured results with modulated 20MHz +30 dBm signal applied at transmit ports are also shown.

2018

1. 

   A 2.5-GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks

   Abhishek Kumar, and Sankaran Aniruddhan

   IEEE Transactions on Circuits and Systems I: Regular Papers, Oct 2018

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   Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7-7.5dB and a Tx insertion loss of 3.9-5.6dB. Self-interference cancellation of \textgreater50dB is measured for 20-MHz RF bandwidth in 2.4-2.6-GHz frequency range.

2. A Same-Channel Full-Duplex Receiver Using Direct RF Sampling

   Abhishek Kumar, Radha Krishna Ganti, and Sankaran Aniruddhan

   In 2018 IEEE International Symposium on Circuits and Systems (ISCAS), May 2018

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   Time selective sampling is capable of eliminating strong interference signals without requiring a high linearity receiver front-end. This can be used to implement a full-duplex transceiver front-end by sampling the weak received signal at the zero-crossings of the strong transmitted signal. In this work, we propose a circuit technique to directly sample the received RF signal at the antenna port by exploiting implicit voltage-to-delay conversion occurring in a full-duplex system. The sampler is implemented in a 65 nm CMOS process, and simulation results show a sensitivity of -67 dBm in the presence of a +5.5 dBm Tx signal. The received signal has a 10 MHz bandwidth, and the overall receiver consumes 33.2 mW from a 1.2 V power supply.

3. A passive RF impedance tuner for 2.4 GHz ISM band applications

   Satyam Sinha, Abhishek Kumar, and Sankaran Aniruddhan

   In 2018 IEEE 19th Wireless and Microwave Technology Conference (WAMICON), Apr 2018

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   This paper presents the design of a passive RF matching network that can be tuned electronically to match a variable load impedance to a fixed source in the 2.4 GHz Industrial, Scientific and Medical (ISM) band. In principle, the design aims at maximum power transfer between the source and the load at any given frequency within the specified range. Theoretical analysis and simulation results have been presented to provide insight into the design of the pi-network circuit. An impedance tuner based on this theory was fabricated on a two-layered FR4 PCB. The fabricated tuner was tested for load impedances up to voltage standing wave ratio (VSWR) ≤ 6, wherein a maximum insertion loss of 4.1 dB was obtained at 2.45 GHz. A maximum insertion loss of 1.7 dB was observed for impedances up to VSWR ≤ 2.4.

2016

1. 

   An Asymmetric 2.4 GHz Directional Coupler Using Electrical Balance

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   IEEE Microwave and Wireless Components Letters, Dec 2016

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   The concept of electrical balance is used to achieve wideband isolation in an asymmetric 2.4 GHz directional coupler. An intuitive approach using impedance transformation property of transmission lines is used to develop the theory for designing arbitrary-coupling-ratio directional couplers. A coupler based on this theory is designed and fabricated on a two-layered RO4003C PCB. The coupler achieves a return loss of better than 10 dB over a 1.7-2.7 GHz range. The transmission coefficients of the strongly and weakly coupled ports are around -3.5 dB and -5 dB respectively, at 2.4 GHz. The isolation is better than 25 dB over a 1.4-3 GHz range.

2015

1. A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

   R. R. Manikandan, Abhishek Kumar, and Bharadwaj Amrutur

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Apr 2015

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   A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-μm CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

2014

1. Directional coupler with high isolation bandwidth using electrical balance

   Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti

   In 2014 IEEE MTT-S International Microwave Symposium (IMS2014), Jun 2014

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   A directional coupler using edge coupled lines is designed and fabricated on a two-layer PCB with isolation being achieved through electrical balance. Measured results show 4dB coupling and 34dB isolation at a frequency of 2.5GHz with 16% matching bandwidth (-10dB). Isolation varies between 31dB to 36dB in the 2.3GHz to 3GHz frequency range.

2. Ground-bounce reduction in narrow-band RF front-ends

   Abhishek Kumar, and Sankaran Aniruddhan

   In 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Jun 2014

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   Ground-bounce due to bond wire inductance is a well known problem in Radio-Frequency (RF) Integrated Circuits. In this paper we propose the use of series resonance with an extra bond wire to substantially reduce ground-bounce effects in narrowband RF front-ends. Instability caused by the ground bond wire is also tackled. Impedance balancing of output stage to null ground-bounce due to other on-chip circuitry is discussed. The proposed techniques are applied to the design of a power amplifier (PA) for 2.5GHz applications and detailed simulations are performed to support the same.